Introduction to the special issue on Networks-on-Chip (NoC) of the Journal of Parallel and Distributed Computing (JPDC)

It is with great pleasure that we introduce the special issue on Networks-on-Chip (NoC) to the readers of the Journal of Parallel and Distributed Computing (JPDC). This special issue consists of eight peer-reviewed papers that cover a wide spectrum of topics in NoC design. Large multicore-based and multiprocessor-based systems-onchip (MPSoC) architectures will easily consist of billions of transistors according to projected technology roadmaps. The complexity in integrating hundreds of cores running simultaneously on a single chip calls for a serious need to revisit the on-chip communication infrastructure. The new on-chip communication paradigm that can effectively address and overcome the design issues is called theNetworks-on-Chip (NoC) paradigm. This special issue focuses on how to meet some of the design challenges posed by current and future NoCs in scalable multicore architectures. The NoC paradigm provides the scalable infrastructure with which we can integrate a large number of computational logic and storage blocks on a single chip. While traditional bus-based networks and point-to-point networks can provide communication bandwidth, they suffer from increased power dissipation and contention or latency issues. Therefore, the NoC paradigm has evolved from the desire to have an infrastructure that can be easily scaled and modularly expanded. With modular and regular communication paths, NoCs enable path diversity, reusability and predictability, which, when combined, reduce network congestion, alleviate power dissipation, and provide enhanced reliability. Mobile handsets, wireless chipsets, portable multimedia and cell phones are just a few applications which make use of MPSoC. In these energy-constrained environments, performance, power consumption and delivery, reliability, fault tolerance, error recovery and hardware costs of the underlying communication fabric (NoC) are posing serious design challenges. Moreover, implementation, testing, yield, modeling and quality of service (QoS) are also related to the practical realization of these systems. With technology scaling, concerns aboutmetallic interconnects for NoC and their scalability into the subnanometer regime are also being debated. With the goal of exploring how the research community is aggressively meeting these challenges, this special issue brings together outstanding experts from both academia and industry who have made significant contributions to the area of NoC design. The first paper in the special section is ‘‘RAFT: A Router Architecture with Frequency Tuning for On-chip Networks’’, by Asit K. Mishra, Aditya Yanamandra, Reetuparna Das, Soumya Eachempati, Ravi Iyer, N. Vijaykrishnan, and Chita R. Das. In this paper, the authors propose to minimize the power dissipation in